1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to CMOS tri-state driver circuit that is powered by a relatively low supply voltage of, for example, 3.3 V, and is capable of driving a common output terminal that can receive external signals at a relatively higher voltage of, for example, 5 V.
2. Description of the Related Art
Continuous advancements in microelectronic integrated circuit fabrication technology enable the geometries of circuit devices to be progressively reduced so that more devices can fit on a single integrated circuit chip. However, certain types of devices are more susceptible to size reduction than other devices. Generally, the geometries of memory circuits are being reduced at a faster rate than are the geometries of logic circuits that are coupled to the memory circuits.
Transistor-Transistor-Logic (TTL) devices are conventionally powered from 5 volt power supplies. However, a problem is encountered in attempting to power memory circuits having smaller feature sizes from a 5 volt power supplies. This is because the upper limit of gate oxide field strength, for the case of silicon dioxide gates, is about 3 MV per centimeter. The maximum allowable voltage across a gate oxide layer of about 150 angstrom thickness is therefore approximately 4 V. If a 5 volt signal is applied to the gate of a small geometry CMOS memory device, the gate oxide can break down and the device can be destroyed.
For this reason, CMOS memory and other devices are being designed for operation with reduced voltage power supplies, a common voltage at the present state of the art being 3.3 V. However, low voltage CMOS memory devices must be operatively interconnected to TTL logic and other devices that operate at supply voltages of 5 V. Often, these devices must be connected to a common input/output line.
3.3 volt CMOS devices are capable of driving 5 volt TTL devices. Generally, such a CMOS device is provided with a tristate output driver circuit that is selectively operable in a normal drive mode, and also in a tristate or high impedance mode in which the driver circuit appears transparent to the line or output terminal to which it is connected.
If no precautions are taken, a 5 volt TTL level signal applied to a line to which a 3.3 volt tristate driver is connected can cause destruction of the driver due to the gate oxide breakdown effect discussed above. To prevent this, several expedients have been proposed in the prior art.
A first example of a prior art 3.3 volt driver circuit that is capable of driving a line common to 5 volt TTL signals is illustrated in FIG. 1 and generally designated by the reference numeral 10.
The driver circuit 10 comprises a pre-driver 12, which receives an input signal A that can have either a logically high value (substantially equal to a power supply voltage VDD=3.3 V), or a logically low value (ground). The pre-driver 12 produces output signals V.sub.p and V.sub.n that are connected to the gates of a PMOS pull up transistor PT1 and an NMOS pull down transistor NT1, respectively. The drain of the transistor PT1 is connected to the drain of the transistor NT1. The source of the transistor PT1 is connected to the power supply voltage VDD, whereas the source of the transistor NT1 is connected to ground.
The common connection of the transistors PT1 and NT1 constitutes an output of the circuit 10, which is applied through a pass-gate consisting of an NMOS transistor NT2 to an output terminal Z. The gate of the transistor NT2 is connected to the supply voltage VDD.
In operation, if a logically high signal A is applied to the pre-driver 12, the signals V.sub.p and V.sub.n will both be logically low. The low signal applied to the gate of the PMOS transistor PT1 turns on the transistor PT1, thereby "pulling up" the junction of the transistors PT1 and NT1 to the supply voltage VDD. The low V.sub.n signal which is applied to the gate of the transistor NT1 turns off the transistor NT1.
Conversely, if the input signal A is low, the signals V.sub.p and V.sub.n will be high. The high V.sub.p signal turns off the transistor PT1. The high signal V.sub.n turns on the transistor NT1. The transistor NT1 "pulls down" the junction of the transistors PT1 and NT1 to ground.
The pass gate transistor NT2 is provided to connect the junction of the transistors PT1 and NT1 to the output Z, and also to protect the transistors PT1 and NT1 from damage which might otherwise result from application of a 5 volt signal from the output terminal Z to the junction of the transistors PT1 and NT1.
More specifically, the power supply voltage VDD=3.3 V is applied to the gate of the transistor NT2. Assuming that a 5 V signal is applied to the terminal Z, the voltage difference between the output terminal and the gate of the transistor NT2 is 5-3.3=1.7 V. If the voltage at the junction of the transistors PT1 and NT1 is zero, the voltage difference between the junction and the gate of the transistor NT2 is 3.3 V. These are the maximum voltage differences that can exist in the circuit 10, and are below the 4 volt limit above which destruction of the transistors PT1, NT1 and/or NT2 can occur.
Although accomplishing its function of protecting the transistors PT1 and NT1 from damage caused by application of 5 V to the output terminal Z, the pass-gate transistor NT2 undesirably limits the output voltage and drive power of the circuit.
Since 3.3 V is applied to the gate of the transistor NT2, the maximum output voltage that the circuit 10 can produce on the output terminal Z is 3.3 V minus the threshold voltage of the transistor NT2, which is typically 0.7 V. The maximum output voltage is therefore 3.3 V-0.7 V=2.6 V. This is only marginally higher than the minimum logically high output level of 2.45 V that is required by TTL logic devices.
If the power supply voltage VDD drops by 10% to 3 V, which is common in actual circuit applications, the output voltage will drop to 3 V-0.7 V=2.3 V, which is too low to drive a TTL logic gate. The drive power of the circuit 10 is correspondingly low.
Although this problem can be solved by applying a higher voltage, for example 4 V, to the gate of the transistor PT1, this is not desirable because an additional power supply would be required to produce this voltage.
FIG. 2 illustrates another driver circuit 20 such as disclosed in U.S. Pat. No. 5,151,619, entitled "CMOS OFF CHIP DRIVER CIRCUIT", issued Sep. 29, 1992 to John Austin et al, that improves over the circuit of FIG. 1 by providing increased output voltage. The circuit 20 comprises a predriver 22 which is similar to the predriver 12 of FIG. 1, but is additionally provided with an enable input EN.
When the input EN is low, the circuit 20 operates in a normal drive mode as described above. When the input EN is high, the circuit 20 operates in a tri-state or high impedance mode, in which it presents an extremely high impedance to the output terminal Z and thereby appears transparent to an external device (not shown) connected to the terminal Z.
The predriver 22 produces output signals V.sub.p and V.sub.n that are connected to the gates of a PMOS pull-up transistor PT2 and an NMOS pull-down transistor NT3, respectively. The transistors PT2 and NT3 correspond to the transistors PT1 and NT1 of the circuit 10, and operate in the manner described above in response to high and low input signals A applied thereto in drive mode. However, due to the absence of a pass-gate, the circuit 20 is capable of providing a high logical output of VDD=3.3 V.
When the enable signal EN is high, the predriver 22 produces high and low signals V.sub.p and V.sub.n that turn off the transistors PT2 and NT3 respectively and produce the high impedance state.
If no precautions are taken and a voltage higher than 3.3 V (for example 5 V) is applied to the output terminal Z by an external TTL logic or other device (not shown), leakage current can flow through the channel of the transistor PT2.
This will occur when the voltage at the terminal Z (the drain of the transistor PT2) exceeds the voltage VDD at the source of the transistor PT2, or when the voltage at the terminal Z is higher than 3.3 V. Current leaks from the terminal Z through the channel of the transistor PT2 from the drain to the source thereof and flows into the source of the voltage VDD.
This undesired current flow is prevented by connecting a PMOS transistor PT4 between the gate and drain of the transistor PT2. The gate of the transistor PT4 is connected to VDD. Whenever the voltage at the terminal Z exceeds VDD plus the threshold voltage of the transistor PT4, or 3.3 V+0.7 V=4.0 V, the transistor PT4 turns on to connect or short the gate and drain of the transistor PT2 together and thereby turn off the transistor PT2.
This arrangement suffers from the drawback that leakage current will flow when the voltage at the terminal Z is between 3.3 V and 4.0 V.
As is conventional in the fabrication of CMOS integrated circuits, PMOS transistors are formed in N-wells (typically all of the PMOS transistors of the circuit 20 are formed in a common N-well) and have substrate terminals that are electrically integral with or connected to the N-well(s). This is not explicitly shown in the present drawings, but is described and illustrated in the above referenced patent to Austin et al.
Due to the N-well construction of the PMOS transistors, a parasitic PN semiconductor junction exists between the drain and N-well of the transistor PT2. If the voltage at the terminal Z exceeds the supply voltage VDD by more than the threshold voltage (typically 0.3 V) of the parasitic junction, leakage current can flow from the terminal Z through the junction into the N-well. With the N-well connected to VDD, this leakage current can flow when the voltage at the terminal Z exceeds 3.3+0.3=3.6 V.
Leakage current is prevented from flowing through the junction by connecting a PMOS switch transistor PT3 between the supply voltage VDD and the substrate terminal (N-well) of the pull-up transistor PT2. The gate of the transistor PT3 is connected to the output terminal Z. The substrate terminal of the transistor PT3 is connected to the substrate terminal (common N-well) of the transistor PT2.
Whenever the voltage at the terminal Z is below VDD minus the threshold voltage of the transistor PT3, or VDD-0.7 V=2.6 V, the transistor PT3 is turned on to connect the substrate terminal of the pull-up transistor PT2 to the supply voltage VDD.
When the voltage at the terminal Z exceeds 2.6 V, the transistor PT3 is turned off and the substrate terminal of the transistor PT2 is allowed to float.
The N-well of the transistors PT2 and PT3 will charge through the parasitic junction to the voltage at the terminal Z minus the threshold voltage of the junction. For a 5 V signal at the terminal Z, the N-well will charge to 5 V-0.3 V=4.7 V. Since the N-well is connected to the substrate terminal of the transistor PT2, this high voltage will turn off the transistor PT2 and prevent further current from flowing from the terminal Z into the N-well.
Another problem is inherent in the circuit 20, however, in that the transistor PT3 will disconnect the substrate terminal of the transistor PT2 from the supply voltage VDD, and allow the substrate terminal to float in drive mode whenever the voltage at the terminal Z exceeds 2.6 V. This causes the N-well to discharge from VDD to a lower voltage, and degrades the drive power and stability of the transistor PT2.